XA6SLX25-2CSG324Q (kūʻai ʻia mai ke kumu kūʻai me ka pahu kumu)

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Hāʻawi ka Xilinx Automotive (XA) Spartan®-6 ʻohana o FPGA i nā mana hoʻohui ʻōnaehana alakaʻi me ka uku haʻahaʻa haʻahaʻa no nā noi automotive kiʻekiʻe.Hāʻawi ka ʻohana he ʻumi i nā densities i hoʻonui ʻia mai ka 3,840 a i ka 101,261 mau cell logic a ʻoi aku ka wikiwiki o ka hoʻohui ʻana.Kūkulu ʻia ma luna o kahi ʻenehana hana keleawe haʻahaʻa haʻahaʻa 45 nm e hāʻawi i ke koena maikaʻi loa o ke kumukūʻai, ka mana, a me ka hana, hāʻawi ka ʻohana XA Spartan-6 i kahi papa ʻike 6-input look-up hou a ʻoi aku ka maikaʻi (LUT). ) logic a me kahi koho waiwai o nā poloka pae ʻōnaehana i kūkulu ʻia.Loaʻa kēia mau mea he 18 Kb (2 x 9 Kb) poloka RAM, nā ʻāpana DSP48A1 lua o ka hanauna, nā mea hoʻomanaʻo SDRAM, nā poloka hoʻokele uʻi hui pū ʻia, ka ʻenehana SelectIO™, nā poloka transceiver serial kiʻekiʻe kiʻekiʻe i hoʻopaʻa ʻia, nā poloka Endpoint kūpono ʻo PCI Express®. , nā ʻano hoʻokele mana o ka ʻōnaehana pae kiʻekiʻe, nā koho hoʻonohonoho hoʻonohonoho ʻokoʻa, a me ka palekana IP i hoʻonui ʻia me ka pale AES a me ka Pūnaewele DNA.Hāʻawi kēia mau hiʻohiʻona i kahi koho programmable haʻahaʻa haʻahaʻa i nā huahana ASIC maʻamau me ka maʻalahi o ka hoʻohana ʻana.Hāʻawi ʻo XA Spartan-6 FPGA i ka hoʻonā maikaʻi loa no nā hoʻolālā logic leo kiʻekiʻe a hiki ke hoʻololi ʻia, nā hoʻolālā hoʻolālā DSP like me ka bandwidth kiʻekiʻe, a me nā noi koʻikoʻi koʻikoʻi kahi e koi ʻia ai nā kūlana interfacing he nui.ʻO XA Spartan-6 FPGAs ka papahana silikona papahana no Targeted Design Platforms e hāʻawi ana i nā lako polokalamu i hoʻohui ʻia a me nā ʻāpana lako e hiki ai i nā mea hoʻolālā ke nānā aku i nā mea hou i ka wā e hoʻomaka ai kā lākou pōʻai hoʻomohala.Hōʻuluʻulu manaʻo o XA Spartan-6 FPGA mau hiʻohiʻona • XA Spartan-6 ʻohana: • XA Spartan-6 LX FPGA: Logic optimized • XA Spartan-6 LXT FPGA: High-speed serial connectivity • Automotive Temperatures: • I-Grade: Tj = – 40°C i +100°C • Q-Grade: Tj = –40°C a i +125°C • Nā Kūlana Automotive: • ʻO Xilinx ka ISO-TS16949 kūpono • AEC-Q100 qualification • Production Part Approval Process (PPAP) palapala • Ma waho aʻe o ka hōʻailona AEC-Q100 i loaʻa ma ke noi • Hoʻolālā ʻia no ke kumu kūʻai haʻahaʻa • Nui nā poloka i hoʻohui ʻia maikaʻi ʻia • koho maikaʻi ʻia o nā kūlana I / O • Staggered pads • Kiʻekiʻe-volume plastic uea-paʻa pūʻolo • Low static a me ka mana ikaika • 45 nm kaʻina hana optimized no ke kumukūʻai a me ka mana haʻahaʻa. • Nā panakō pili SelectIO maʻamau a nui-voltage, multi-standard • A hiki i ka 1,080 Mb/s ka helu hoʻoili ʻikepili no kēlā me kēiaʻokoʻa I/O • koho ʻia ka hoʻokuʻu ʻana, a hiki i ka 24 mA ma kēlā me kēia pine • 3.3V a i 1.2VI/O maʻamau a me nā protocols • Haʻahaʻa kumu kūʻai HSTL a me SSTL hoʻomanaʻo pānaʻi • Hoʻololi hoʻololi wela • Hiki ke hoʻololi ʻia nā helu pepehi I/O e hoʻomaikaʻi i ka pono o ka hōʻailona. • Nā transceivers serial GTP kiʻekiʻe i loko o nā FPGA LXT • A hiki i 3.2 Gb/s • Nā pilina kiʻekiʻe me: Serial ATA a me PCI Express • Nā ʻāpana DSP48A1 maikaʻi • Kiʻekiʻe-hana helu a me ka hōʻailona hana • wikiwiki 18 x 18 multiplier a me 48 -bit accumulator • Pipelining and cascading capability • Pre-adder e kōkua i nā noi kānana • Integrated Memory Controller blocks • DDR, DDR2, DDR3, a me LPDDR kākoʻo • Nā helu ʻikepili a hiki i 800 Mb/s • Multi-port bus structure with independent FIFO to e ho'ēmi i nā pilikia o ka manawa hoʻolālā • Nui nā kumu waiwai noʻonoʻo me ka hiki ke hoʻonui i ka loiloi • Kākau hoʻololi koho a i ʻole kākoʻo RAM puʻunaue ʻia • Hoʻomaikaʻi maikaʻi nā LUT 6-input maikaʻi i ka hana a hoʻemi i ka mana • LUT me ʻelua flip-flops no nā noi pipeline centric • Block RAM with ka laula o ka granularity • Fast block RAM me byte write enable • 18 Kb blocks i hiki ke koho ʻia e like me ʻelua kūʻokoʻa 9 Kb block RAMs • Clock Management Tile (CMT) no ka hoʻomaikaʻi ʻana i ka hana. (DCMs) e hoopau i ka wili o ka uaki a me ke kaapuni hana • Phase-Locked Loops (PLLs) no ka wati ha'aha'a. nā kumu kūʻai • 2-pin auto-detect configuration • Broad kolu-aoao SPI (a hiki i x4) a me NOR flash kākoʻo • MultiBoot kākoʻo no ka mamao hoʻonui me nā bitstreams he nui, me ka hoʻohana 'ana i ka kiaʻi pale • Hoʻonui i ka palekana no ka hoʻolālā hoʻolālā • Unique Device DNA identifier no hōʻoia manaʻo • AES bitstream encryption ma XA6SLX75, XA6SLX75T, a me XA6SLX100 mea hana • Integrated Endpoint block no PCI Express designs (LXT) • Haʻahaʻa kumu kūʻai ʻenehana PCI® support kūpono me ka 33 MHz, 32- a me 64-bit kiko'ī.• ʻOi aku ka wikiwiki i hoʻokomo ʻia me ka hoʻonui ʻia, ke kumu kūʻai haʻahaʻa, MicroBlaze™ 32-bit soft processor • IP alakaʻi alakaʻi ʻoihana a me nā hoʻolālā kuhikuhi • ʻO ka kaiaola kaiaola ʻokoʻa ʻokoʻa me ka IP, nā papa hoʻomohala, a me nā lawelawe hoʻolālā.