XC7Z020

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Kaiapuni a me ka hoʻokuʻu ʻia ʻana:

ʻO Zynq-7000 SoC Hoʻolālā Hana Hou:
Hoʻokumu ʻia ka ʻohana Zynq®-7000 ma ka hoʻolālā Xilinx SoC.Hoʻohui kēia mau huahana i kahi ʻōnaehana hoʻoponopono hoʻonohonoho pono ʻelua-nui a i ʻole hoʻokahi-core ARM® Cortex™-A9 (PS) a me 28 nm Xilinx programmable logic (PL) i hoʻokahi mea.ʻO ka ARM Cortex-A9 CPUs ka puʻuwai o ka PS a loaʻa pū kekahi me ka hoʻomanaʻo ma luna o ka chip, nā mea hoʻomanaʻo hoʻomanaʻo waho, a me kahi pūʻulu waiwai o nā pilina pili peripheral.Pūnaehana Hana (PS) ARM Cortex-A9 Pūnaehana Kaʻina Hana Hana (APU) • 2.5 DMIPS/MHz no kēlā me kēia CPU • ʻO ke alapine CPU: A hiki i 1 GHz • Kākoʻo multiprocessor paʻa • ARMv7-A architecture • TrustZone® palekana • Thumb®-2 aʻo hoʻonohonoho • Jazelle® RCT execution Environment Architecture • NEON™ media-processing engine • Single and double precision Vector Floating Point Unit (VFPU) • CoreSight™ and Program Trace Macrocell (PTM) • Timer and Interrupts • ʻEkolu mau kiaʻi manawa • Hoʻokahi manawa honua • ʻElua mau helu helu ʻekolu manawa ʻelua Caches • 32 KB Level 1 4-way set-associative instruction and data caches (kūʻokoʻa no kēlā me kēia CPU) • 512 KB 8-way set-associative Level 2 cache (kaʻana like ma waena o nā CPU) • Kākoʻo Byte-parity Hoʻomanaʻo ma luna o ka puʻupuʻu • ROM pahu pahu ma luna o ka chip • 256 KB RAM ma luna o ka chip (OCM) • Kākoʻo Byte-parity Nā Interface Hoʻomanaʻo Kūwaho • Multiprotocol dynamic memory controller • 16-bit a i ʻole 32-bit interface i DDR3, DDR3L, DDR2, a i ʻole Nā hoʻomanaʻo LPDDR2 • Kākoʻo ECC ma ke ʻano 16-bit • 1GB o ka helu wahi me ka hīmeniʻO ke kūlana o 8-, 16-, a i ʻole 32-bit-ākea hoʻomanaʻo • Nā kikowaena hoʻomanaʻo static • 8-bit SRAM data bus me ke kākoʻo a hiki i ka 64 MB • Kākoʻo uila Parallel NOR • Kākoʻo uila ONFI1.0 NAND (1-bit ECC ) • 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), a i ole elua quad-SPI (8-bit) serial NOR flash 8-Channel DMA Controller • Memory-to-memory, memory-to -Kakoʻo pili, peripheral-to-memory, a scatter-gather transaction support I/O Peripherals and Interfaces • ʻElua 10/100/1000 tri-speed Ethernet MAC peripherals me IEEE Std 802.3 a me IEEE Std 1588 revision 2.0 kākoʻo • Scatter-hui DMA hiki • 'ike i ka 1588 rev.2 PTP papa • GMII, RGMII, a me SGMII interface • Elua USB 2.0 OTG peripherals, kēlā me kēia kākoʻo a hiki i 12 Endpoints • USB 2.0 compliant IP IP core • Kākoʻo ma ka hele, kiʻekiʻe-wikiwiki, piha-wikiwiki, a haʻahaʻa- nā ʻano wikiwiki • Intel EHCI hoʻokō USB host • 8-bit ULPI waho PHY interface • ʻElua piha CAN 2.0B hoʻokō CAN kaʻaahi interface • CAN 2.0-A a me CAN 2.0-B a me ISO 118981-1 paʻa pono • waho PHY interface • ʻElua SD /SDIO 2.0/MMC3.31 nā mea hoʻoponopono hoʻoponopono • ʻElua mau awa SPI piha-duplex me ʻekolu mau puʻupuʻu peripheral koho • ʻElua UART kiʻekiʻe-wikiwiki (hiki i 1 Mb/s) • ʻElua haku a me ke kauā I2C interface • GPIO me ʻehā mau panakō 32-bit , a hiki i ka 54 bits hiki ke hoohana me ka PS I/O (hookahi panaka o 32b a me hookahi panakō o 22b) a hiki i 64 bits (a hiki i elua panakō o 32b) pili i ka Programmable Logic • A hiki i 54 flexible I/O (MIO) i hoʻohui ʻia no nā hana pin peripheral Interconnect • Hoʻohui ʻana i ka bandwidth kiʻekiʻe i loko o PS a ma waena o PS a me PL • ARM AMBA® AXI i hoʻokumu ʻia • Kākoʻo QoS ma ka critical haku no ka latency a me ka bana.